1. Field of the Invention
The present invention relates to a decoder that outputs a signal to the output port corresponding the combination of input signals applied, in particular, to a decoder using a level shifter that improves economy by reducing the area occupied in the chip and by increasing the operational speed.
2. Description of the Prior Art
In general, the decoder, which is used as a typical function circuit for the combination of gates within various digital systems such as 1-chip microprocessors, custom integrated circuit (IC's), and controllers for electrical devices, performs the role of finding the memory address by decoding the data from various combinations of signals. Therefore, the decoder that is used within a digital system as a function circuit for control purposes consists of a combination of several complementary metal oxide semiconductor NAND or NOR gates, which occupy a large area of semiconductor chip. As a result, the unit price and yields can be affected, since the decoder occupies a large portion of the digital system and, accordingly, the circuit operates with limited speed of operation.
For example, as shown in FIG. 1, let's consider a 3-input decoder composed of CMOS NOR gates. In the circuit, based upon each combination of the 3 input signals A,B, and C, 8 NOR gates are requisite to find a specific bit line using the decoder, because we must select a specific piece of data out of 8 outputs 01 thorugh 08. In this case, three p-channel transistors should be connected in parallel with the serially connected three n-channel transistors per NOR gate; hence six transistors are required in total. In the line run, a total of 48 transistors are used in a 3-input decoder. In the case of a 4-input decoder, not only is a combination of 96 transistors and their corresponding area required, but there is also the disadvantage of having limited operational speed, since the speed of setting an output for the 3-input decoder corresponds to the delay time of the three p-channel transistors.